Phase 3 core memory substrate

Phase 3 — Tracks

Five execution tracks for the core memory substrate.

Phase 3 — Tracks

Track A — Schema & Migrations

Memory schema with temporal validity, multi-label categories, and HNSW-ready vector columns. Schema details are a planning baseline and may be refined during implementation.

Preferred sequencing within track: single foundation milestone; blocks Tracks B–D. Status: 3.1.1 completed (ADR-0052 / 000017).

Track B — Vector Store & Embedding

Pluggable vector store interface with pgvector HNSW as the starting backend preference (replacing the earlier IVFFlat plan). Alternatives can be investigated if latency/recall measurements require it.

Preferred sequencing within track: depends on Track A schema.

Track C — Write Pipeline

Memory write pipeline stages: validate → PII detect/redact → dedup → embed → near-dup → conflict detect → DB write → cache update → index. Stage order is the preferred starting sequence and can be adjusted after integration testing.

Preferred sequencing within track: 3.C.1 → 3.C.2 → 3.C.3 → 3.C.4 after Tracks A/B.

Track D — Read/Ranking Pipeline

Semantic search read path, composite scoring with category-conditional decay, and Redis sorted-set hot cache.

Preferred sequencing within track: 3.D.1 → 3.D.2 → 3.D.3 after Track B.

Track E — Exit Gate

Security integration suite, E2E lifecycle test, retrieval-quality benchmark, ADR consolidation, and exit audit.

Preferred sequencing within track: 3.E.1 → 3.E.2 → 3.E.3 → 3.E.4 → 3.E.5 after Tracks A–D.

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